1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage apparatus and a method of manufacturing the same, and in particular, to a structure of a source wiring layer in a cell array of a NOR type nonvolatile semiconductor memory and a method of manufacturing the same.
2. Description of the Related Art
FIG. 1 shows an equivalent circuit of a part of a cell array of a NOR type flash memory of a floating gate structure. FIG. 2 shows a layout of the cell array of the NOR type flash memory in FIG. 1.
The NOR type cell array shown in FIGS. 1 and 2 is formed of a plurality of memory cells MC arranged in a matrix form in a well region formed in a surface layer of a semiconductor substrate. Each of the memory cells MC comprises a cell transistor. The cell transistor comprises an active region (i.e., impurity diffusion layers for source/drain and a channel layer) formed in the well region, and a two-layer gate structure (i.e., a structure in which a control gate is formed on a floating gate via an inter-gate insulating film) via an gate insulating film on the well region.
In the above-described NOR type cell array, two adjacent memory cells in a column direction combine to form a set of memory cells, and the two adjacent memory cells share a drain region D. Two adjacent sets of the two adjacent memory cells in the column direction share a source region S. Columns of the memory cells are separated from each other by a shallow trench type isolation (STI) region.
A plurality of word lines WL are arranged on the cell array in a row direction. Each of the word lines WL is commonly connected to control gate electrodes of the memory cells on a corresponding row.
A plurality of local source lines LS are arranged on the cell array in the row direction. Each of the local source lines LS is formed of a metal wiring layer and commonly connected to the shared source regions S of the memory cells on a corresponding row.
Further, a plurality of bit lines BL, which are formed of metal wiring layers and thus low in resistance, are arranged on the cell array in the column direction. Each of the bit lines BL is commonly connected to the shared drain regions D of the memory cells on a corresponding column.
A plurality of main source lines MS, which are formed of metal wiring layers and thus low in resistance, are intermittently arranged in the column direction between the arrangements of the bit lines BL, although in FIGS. 1 and 2, only one main source line MS is shown. Each of the main source lines MS is commonly connected to the plurality of local source lines LS.
As described above, the drains D of the same column, each shared by the two memory cells forming a memory cell set in the column direction, are commonly connected to the low resistance bit line BL via drain contacts DC. Further, the sources S, each shared by adjacent two sets of memory cells in the column direction, are connected to the local source line LS extending in parallel to and between two adjacent word lines WL. The local source line LS is connected to the main source MS of a low resistance via a source line contact SC, and is supplied with an electric potential from the outside of the cell array.
In the NOR type flash memory having the above-described configuration, when an electron injection is carried out to inject electrons into a floating gate by using a channel hot electron injection to write data to the cell, ground potential is applied to the source S and the well region of the cell. Further, predetermined potentials by which the generation efficiency of hot electrons are made maximum are applied to the control gate and the drain D via the word line WL and the bit line BL, respectively, from an external circuit.
In such an electron injecting method using the channel hot electrons, a sufficient writing of data into the cell is obtained only when a large electric current is flown through the source and the drain of the cell, since the electron injection efficiency into the floating gate is low. Accordingly, it is desirable that the source and the drain of the cell be connected to a predetermined potential via a low resistance.
However, since the source wiring layer is formed of the local source line LS of a high resistance and the main source line MS of a low resistance, the wiring length is long, and the resistance of the source wiring layer up to the source of the cell is large. Since a large electric current flows in the source wiring layer at the time of writing data, the resistance of the source wiring layer can not be negligible, and a rise of the source electric potential of the selected cell (a rise in the electric potential of the local source line) arises, which makes the writing insufficient.
In particular, when data writings are simultaneously carried out to a plurality of cells by selecting a plurality of bit lines BL at the same time, electric current for writing data to the plurality of cells flows simultaneously into the same source line. Therefore, a rise in the electric potential of the source line is made large, and a significant deterioration in the writing characteristic is brought about.
In order to solve the problem, it can be thought that a rise in the electric potential of the source line is suppressed by increasing electric contact points between the low resistance main source line MS and the local source line LS, i.e., by making intervals among the adjacent source lines MS small, to make the wiring length of the local source line relatively short. However, the more the number of the main source lines increases, the more the area of the cell array increases.
In “Semiconductor Integrated Circuit” in Jpn. Pat. Appln. KOKAI Publication No. 2000-269467 (FIGS. 1 and 2), there is disclosed a technique in which a recess portion is formed in the STI region by etching the STI region up to a position lower than the surface of the element region to expose the n-type source regions of both sides of the STI region, and a wiring conductor layer (local source line) is embedded in the recess portion to electrically connect the exposed n-type source regions at the both sides of the region STI to each other.
As described above, in convention, there has been the problem that since the route of the source wiring layer is long, the resistance of the source wiring layer up to the source of the cell is made high, floating of the electric potential arises at the source portion of the selected cell at the time of writing, and the writing characteristic deteriorates.